A power supply mounted on an electronic apparatus steps down an external voltage to a level appropriate for the electronic circuit in the apparatus. Power efficiency of some of such power supplies varies depending on the loading condition of the output terminal of the power supply. For example, a DC-DC converter that steps down the voltage by means of PWM control exhibits low power efficiency when the loading is light and high power efficiency when the loading is heavy. This is due to driving losses generated at the ON-OFF operation of semiconductor switches in the DC-DC converter. On the other hand, a series regulator performs at constant power efficiency independently of the loading.
There are known power supply systems that exchange a power source between a DC-DC converter and a series regulator corresponding to the loading, as disclosed in Japanese Unexamined Patent Application Publication No. H11-341797 and No. 2002-112457. When the load connected to the power supply system is light, the series regulator steps down the voltage. When the load connected to the power supply system is heavy, as the power efficiency of a DC-DC converter is higher than the power efficiency of the series regulator, the DC-DC converter steps down the voltage. This type of a power supply system is mounted, for example, on an electronic apparatus that operates in a waiting mode and a normal operating mode. In the waiting mode, the number of driven circuits are small, making the loading light so that the series regulator can step down the voltage. In the normal operating mode, a larger number of circuits are driven, increasing the loading so that the DC-DC converter can step down the voltage.
FIG. 6 shows a circuit diagram of a conventional power supply system. The power supply system of FIG. 6 comprises a DC-DC converter 40 and a series regulator 50 connected parallel to the DC-DC converter 40. Output terminals of the DC-DC converter 40 and the series regulator 50 connect to a capacitor C3 and a load 60. The DC-DC converter 40 operates upon receipt of an enable signal EN1. The series regulator 50 operates upon receipt of an enable signal EN2. The enable signals EN1 or EN2 is fed to the DC-DC converter 40 or the series regulator 50 depending on the loading condition of the load 60. When the load 60 is light, the enable signal EN2 is fed to the series regulator 50. When the load 60 becomes heavy and the power efficiency of the DC-DC converter exceeds the power efficiency of the series regulator 50, the enable signal EN1 is fed to the DC-DC converter 40.
The DC-DC converter 40 comprises a PWM control circuit 41, drivers Z3 and Z4, transistors Q3 and Q4, diodes D3 and D4, and an inductor L3. The DC-DC converter 40 is a synchronous step-down DC-DC converter. In the synchronous rectification system, the diode used as a rectifying element in the conventional system that would be disposed at the position of the transistor Q4 is replaced by a transistor Q4, which has lower ON-resistance. The transistors Q3 and Q4 complementarily turn ON and OFF, and control the output voltage by a duty cycle of the transistor Q3. Conduction losses can be reduced by using the transistor Q4 with low ON-resistance in place of a diode. The PWM control circuit 41 receives a feed back voltage at a terminal of the inductor L3 and outputs switching signals OUT1 and OUT2 that are pulse-width-modulated in response to the feed back voltage. The drivers Z3 and Z4 drive the transistors Q3 and Q4 in response to the switching signals OUT1 and OUT2 output from the PWM control circuit 41. The transistor Q3 is an N-channel MOS transistor. When a switching signal OUT1 at a high level, that is, in an ‘H’ state, is fed to the gate, the transistor Q3 turns on between the source and the drain thereof, and transfers the input voltage Vin to the inductor L3. A parasitic diode D3 of the transistor Q3 is connected between the source and the drain of the transistor Q3. The transistor Q4 is an N-channel MOS transistor. When a switching signal OUT2 at an ‘H’ state is fed to the gate, the transistor Q4 turns ON between the source and the drain thereof, and connects the inductor L3 to the ground. A parasitic diode D4 of the transistor Q4 is connected between the source and the drain of the transistor Q4.
FIG. 7 is a timing chart showing an enable signal fed to the PWM control circuit and output signals output from the PWM control circuit. The PWM control circuit 41 outputs switching signals OUT1 and OUT2 upon transition of the enable signal EN1 from the ‘L’ state to the ‘H’ state, as shown in FIG. 7. The switching signals OUT1 and OUT2 are output in ‘H’ state complementarily. The PWM control circuit 41 outputs switching signals OUT1 and OUT2 intervening a dead time td between ‘H’ states of the switching signals OUT1 and OUT2 in order to prevent the transistors Q3 and Q4 from simultaneously turning ON between the source and the drain of the transistors. The ON-period duty cycle D of the DC-DC converter is represented by the equation (1) below independently of output current.D=Vout/Vin   (1)
When power supply operation is switched from the series regulator to the DC-DC converter, if an initial ON-period duty cycle DO immediately after the power source changeover is smaller than the on-period duty cycle D represented by the equation (1), a period of excessive ON-time of the transistor Q4 is generated during the interval of transition from the initial ON-period duty cycle DO to the ON-period duty cycle D due to delay of the PWM control circuit 41. Accordingly, immediately after changing the power source, the current originating from the charges stored in the capacitor C3 flows back from the capacitor C3 through the inductor L3 and the transistor Q4 to the ground. As a result, the output voltage Vout from the DC-DC converter 40 temporarily decreases significantly. FIG. 8 is a timing chart showing output voltage from the power supply system and enable signals fed to the power supply system. As shown in the FIG. 8, at the time t1, enable signal EN1 is changed from ‘L’ state to ‘H’ state and enable signal EN2 is changed from ‘H’ state to ‘L’ state, to changeover the power source from the series regulator 50 to the DC-DC converter 40. The output voltage Vout from the DC-DC converter 40 temporarily decreases significantly, as illustrated in FIG. 8.
As described above, the problem with the conventional power supply system is that when the power source is changed over from the series regulator 50 to the DC-DC converter 40, the ON-period of the transistor Q4 becomes excessively large, causing a backward current flow through the transistor Q4 to the ground, resulting in drop in the output voltage. Accordingly, there is a need for a power supply system that prevents the output voltage from dropping during the power source changeover from the series regulator to the DC-DC converter. The present invention addresses this need.